A 14-bit current-mode /spl Sigma//spl Delta/ DAC based upon rotated data weighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order /spl Sigma//spl Delta/ digital-to-analog converter (DAC) with 64/spl times/ oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The /spl Sigma//spl Delta/ DAC is fabricated in a 2-/spl mu/m CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA.