Title :
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM
Author :
Nambu, Hiroaki ; Kanetani, Kazuo ; Yamasaki, Kaname ; Higeta, Keiichi ; Usami, Masami ; Nishiyama, Masahiko ; Ohhata, Kenichi ; Arakawa, Fumihiko ; Kusunoki, Takeshi ; Yamaguchi, Kunihiko ; Hotta, Atsuo ; Homma, Noriyuki
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-/spl mu/m/sup 2/ memory cells has been developed using 0.2-/spl mu/m BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers.
Keywords :
BiCMOS memory circuits; SRAM chips; cache storage; cellular arrays; driver circuits; emitter-coupled logic; very high speed integrated circuits; 0.2 micron; 1 Mbit; 550 ps; 900 MHz; BiCMOS technology; ECL-CMOS SRAM; cache; clock-access time; control memories; delay times; level-shift circuit; memory cells; operating frequency; power dissipation; sense amplifier; ultrahigh-speed IC; variable-impedance bitline load; voltage-clamp circuit; word decoder/driver; write circuit; writing speed; BiCMOS integrated circuits; Clocks; Decoding; Delay; Driver circuits; Frequency; Logic; MOS devices; Random access memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
