• DocumentCode
    1370524
  • Title

    A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs

  • Author

    Kono, Takashi ; Hamamoto, Takeshi ; Mitsui, Katsuyoshi ; Konishi, Yasuhiro ; Yoshihara, Tsutomu ; Ozaki, Hideyuki

  • Author_Institution
    ULSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
  • Volume
    35
  • Issue
    8
  • fYear
    2000
  • Firstpage
    1179
  • Lastpage
    1185
  • Abstract
    A precharged capacitor-assisted sensing (PCAS) scheme suitable for low-power DRAM using boosted-sense ground (BSG) is proposed. In this scheme, the data on bitlines are sensed with the assistance of precharged capacitors. Precise data level generation is achieved with sense speed 4.2 ns faster than the conventional scheme in the case that bitline swing is 1.4 V. Necessary decoupling capacitors can be efficiently implemented in memory arrays by using junction capacitors between well and substrate so that the area penalty of decoupling capacitors can be minimized. To keep sensed data stable, two types of level controllers are introduced. A voltage downconverter (VDC) with a current mirror discharger (CMD) compensates for the change of both data levels during write/read operations. A level controller with charge transfer amplifier (CTA) prevents the BSG level from falling during the row active period. The two level controllers greatly improve data-retention characteristics.
  • Keywords
    Capacitors; Cellular arrays; Current mirrors; DRAM chips; Low-power electronics; area penalty; bitline swing; boosted-sense ground; charge transfer amplifier; current mirror discharger; data level generation; data-retention characteristics; decoupling capacitors; junction capacitors; level controllers; low-power DRAMs; memory arrays; precharged-capacitor-assisted sensing scheme; row active period; sense speed; voltage downconverter; write/read operations; Capacitors; Character generation; Charge transfer; Leakage current; Logic circuits; Mirrors; Principal component analysis; Random access memory; Subthreshold current; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.859507
  • Filename
    859507