• DocumentCode
    1370719
  • Title

    On the design of IEEE compliant floating point units

  • Author

    Even, Guy ; Paul, Wolfgang J.

  • Author_Institution
    Dept. of Electr. Eng. Syst., Tel Aviv Univ., Israel
  • Volume
    49
  • Issue
    5
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    398
  • Lastpage
    413
  • Abstract
    Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm
  • Keywords
    floating point arithmetic; logic design; IEEE compliant; IEEE rounding uni; floating point units; floating-point adder; local verification; provably correct; rounding unit; Design engineering; Design methodology;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.859536
  • Filename
    859536