• DocumentCode
    1370760
  • Title

    An architecture for computing Zech´s logarithms in GF(2m)

  • Author

    Assis, F.M. ; Pedreira, C.E.

  • Author_Institution
    Univ. Fed. do Paraiba, Brazil
  • Volume
    49
  • Issue
    5
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    519
  • Lastpage
    524
  • Abstract
    In this paper, a new method for calculation of Zech´s logarithm in GF(2m) is presented. For a given element, the logarithm is calculated by bit operations performed on its binary representation. No look-up tables are used. The proposed method makes feasible the implementation of an universal-type device for finite field arithmetic
  • Keywords
    digital arithmetic; logic design; Zech logarithms; Zech´s logarithm; bit operations; discrete neural networks; finite field arithmetic; finite fields; universal-type device; Computer architecture;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.859543
  • Filename
    859543
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1370760