Very large scale integration architecture for integer wavelet transform

In this study, the design of an integer lifting wavelet transform (IWT) architecture is presented. An efficient design method is proposed to construct a programmable integrated architecture in very large scale integration (VLSI) technology that can operate as a forward or backward IWT at speeds up to 194.3 MHz. The layout of the integrated VLSI structure is simple, modular and cascadable for computing a wavelet transform based on 5/3 biorthogonal filters. The architecture is optimal with respect to both area and time and independent of the size of the input signal without requiring additional memory. The lifting steps are adapted to be causal with the ability to execute lifting steps on a continuous flow of input data samples. The critical path of the architecture is equal to the critical path of one lifting step. The numerical precision and experimental results have been established with 8-bit signed two s complement integer numbers. Based on the experimental results, fixing the wordlength of the proposed architecture at 11 bits gives the best results in both forward and reverse wavelet transform modes.