Title :
Path sensitisation and gate sizing approach to low power optimisation
Author :
Kim, Juho ; Yang, Jaesok ; Hwang, Sun-Young
Author_Institution :
Dept. of Comput. Sci., Sogang Univ., Seoul, South Korea
fDate :
4/2/1998 12:00:00 AM
Abstract :
A powerful circuit optimisation solution for high-performance and low-power design is presented. The proposed method combines path sensitisation and gate resizing approaches to reduce the power dissipation under a given timing constraint. The algorithm is tested on ISCAS-85 benchmark circuits, and up to 30%, power reduction is achieved
Keywords :
circuit layout CAD; circuit optimisation; digital integrated circuits; integrated circuit layout; logic CAD; circuit optimisation solution; gate sizing; low power optimisation; low-power design; path sensitisation; timing constraint;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980473
