DocumentCode
1371274
Title
Configurable multiplier blocks for embedding in FPGAs
Author
Haynes, S.D. ; Cheung, P.Y.K.
Volume
34
Issue
7
fYear
1998
fDate
4/2/1998 12:00:00 AM
Firstpage
638
Lastpage
639
Abstract
A new architecture for configurable blocks is proposed which can be used to construct multipliers. An array of these blocks is capable of being configured to perform any 4m bit×4n bit signed/unsigned binary multiplication. The blocks are designed to be embedded within a conventional FPGA structure to increase the functionality of the device by freeing valuable general reconfigurable resources, particularly when used in the area of image processing
Keywords
field programmable gate arrays; multiplying circuits; reconfigurable architectures; FPGA; binary multiplication; embedded configurable multiplier block array; image processing; reconfigurable architecture;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19980501
Filename
673766
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