Power optimisation of FPGA-based designs without rewiring

A new technique is proposed to perform power-oriented reconfiguration of combinational circuits implemented using look-up table (LUT)-based FPGAs. The main features of this approach are: exploitation of functional flexibilities, concurrent optimisation of multiple LUTs based on Boolean relations, and in-place reprogramming without replacement and rewiring. The tool optimises the combinational component of the configurable logic blocks (CLBs) after layout, and does not necessitate any rerouting or rewiring. Hence, delay and CLB usage are left unchanged, while power is minimised. As the algorithm operates locally on the various LUT clusters of the network, it is applicable and best performs on large examples as demonstrated by our experimental results: an average power reduction of 11.5% has been obtained on standard benchmark circuits