• DocumentCode
    1371329
  • Title

    Design of GF(2m) multiplier using its subfields

  • Author

    Yong Suk ; Park, Sang Kyu

  • Author_Institution
    Dept. of Electron. Commun. Eng., Hanyang Univ., Seoul, South Korea
  • Volume
    34
  • Issue
    7
  • fYear
    1998
  • fDate
    4/2/1998 12:00:00 AM
  • Firstpage
    650
  • Lastpage
    651
  • Abstract
    A design method of a GF(2m) multiplier using its subfields is presented. This method can be used to construct a sequential logic multiplier using a bit-parallel multiplier for its subfield. It has an advantageous feature, namely that a trade-off between hardware complexity and delay time can be achieved
  • Keywords
    delays; multiplying circuits; sequential circuits; GF(2m) multiplier; bit-parallel multiplier; delay time; hardware complexity; sequential logic multiplier; subfields;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19980521
  • Filename
    673775
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1371329