• DocumentCode
    1371342
  • Title

    Dynamic scheduling of tasks on partially reconfigurable FPGAs

  • Author

    Diessel, O. ; ElGindy, H. ; Middendorf, M. ; Schmeck, H. ; Schmidt, B.

  • Author_Institution
    Sch. of Comput. Sci. & Eng., New South Wales Univ., Kensington, NSW, Australia
  • Volume
    147
  • Issue
    3
  • fYear
    2000
  • fDate
    5/1/2000 12:00:00 AM
  • Firstpage
    181
  • Lastpage
    188
  • Abstract
    Field-programmable gate arrays (FPGAs) which allow partial reconfiguration at run time can be shared among multiple independent tasks. When the sequence of tasks to be performed is unpredictable, the FPGA controller needs to make allocation decisions online. Since online allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit noncontiguous, resources available to service them. The time to complete tasks is consequently longer and the utilisation of the FPGA is lower than it could be. It is proposed that a subset of the tasks executing on the FPGA be rearranged when to do so allows the next pending task to be processed sooner. Methods are described and evaluated for overcoming the NP-hard problems of identifying feasible rearrangements and scheduling the rearrangements when moving tasks are reloaded from off-chip
  • Keywords
    computational complexity; field programmable gate arrays; logic arrays; logic design; processor scheduling; NP-hard problems; dynamic scheduling; multiple independent tasks; partially reconfigurable FPGAs;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings -
  • Publisher
    iet
  • ISSN
    1350-2387
  • Type

    jour

  • DOI
    10.1049/ip-cdt:20000485
  • Filename
    860848