High-speed interconnect schemes for a pipelined FPGA

The paper presents two high-speed interconnect schemes for a pipelined FPGA utilising a locally synchronised postcharging technique. By avoiding a global synchronised clock, we reduce the power consumption significantly. Through postcharging the interconnect and overlapping the postcharging delay with the logic delay, we successfully hide the postcharge time. The long channel devices significantly reduce the area penalty due to delay elements. The timing simulation is done using Hspice for a TSMC 0.35 μm and area is measured by drawing key elements in MAGIC and using the area model developed by Betz. The postcharge scheme shows a 30% delay reduction over the precharge scheme and up to 310% and 230% delay reductions over the conventional NMOS pass transistor scheme and the tristate buffer scheme respectively