DocumentCode :
1371886
Title :
An optimum SNS-to-binary conversion algorithm and pipelined field-programmable logic design
Author :
Pace, Phillip E. ; Styer, David ; Ringer, William P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Naval Postgraduate Sch., Monterey, CA, USA
Volume :
47
Issue :
8
fYear :
2000
fDate :
8/1/2000 12:00:00 AM
Firstpage :
736
Lastpage :
745
Abstract :
The Optimum Symmetrical Number System (OSNS) formulation is a direct consequence of the need to extract the maximum amount of information from a symmetrically folded waveform, and has found use in applications such as folding analog-to-digital converters and phase-sampled direction finding antenna architectures. One of the key problems in an OSNS hardware realization is recombining the OSNS symmetrical residues (S1,S2,...S3) to determine the unknown incoming value. The symmetrical residues cannot be converted (e.g., using the Chinese Remainder Theorem) in a straightforward manner, since the integers within each modulus are ambiguous. This paper presents an OSNS-to-binary conversion algorithm for N=3 moduli of the form m1=2k+1, m2=2k, and m3=2k-1. The algorithm consists of three main steps: 1) conversion of the symmetrical residues into complete residues; 2) solving the resulting congruences in binary; and 3) determining the unknown incoming value. A B=14-bit pipelined field-programmable logic design (FPLD) using Fe=6 is also presented to illustrate the algorithm. The number of bits throughout the FPLD are quantified and an example calculation is worked out to numerically demonstrate the efficiency of the design
Keywords :
analogue-digital conversion; field programmable gate arrays; logic CAD; number theory; pipeline processing; radio direction-finding; 14 bit; SNS-to-binary conversion algorithm; congruences; folding analog-to-digital converters; hardware realization; phase-sampled direction finding antenna architectures; pipelined field-programmable logic design; symmetrical number system; symmetrical residues; symmetrically folded waveform; unknown incoming value; Analog-digital conversion; Computational complexity; Data mining; Data preprocessing; Directive antennas; Field programmable gate arrays; Hardware; Laboratories; Logic design; Signal analysis;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.861406
Filename :
861406
Link To Document :
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