Title :
An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface
Author :
Noda, Hiromasa ; Aoki, Masakazu ; Tanaka, Hitoshi ; Nagashima, Osamu ; Aoki, Hideyuki
Author_Institution :
Semicond. & IC Group, Hitachi Ltd., Tokyo, Japan
fDate :
8/1/2000 12:00:00 AM
Abstract :
A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-μm technology demonstrates that a resolution of 26 ps can be achieved. A clock-recovery circuit using this circuit has a two-clock-cycle lock time and sub-100-ps error
Keywords :
DRAM chips; delays; high-speed integrated circuits; synchronisation; 0.35 micron; 26 ps; arrayed delay components; clock-recovery circuit; fine-delay circuit; high-speed DRAM interface; input-coupling element; on-chip clock-adjusting circuit; rail-to-rail delayed signals; two-clock-cycle lock time; Circuit testing; Clocks; Delay; Feedback circuits; Feedback loop; Frequency; Phase locked loops; Random access memory; Sampling methods; Signal resolution;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
