Design and performance evaluation of microprocessor packaging capacitors using integrated capacitor-via-plane model

As clock speeds increase into the gigahertz regime and rise times decrease into the picosecond regime, the interaction between capacitors and power/ground planes of a package, interposer, or board on which they are mounted becomes vitally important to the performance of a power delivery system. To include the interaction, this paper provides an integrated model for a discrete capacitor mounted on pads over vias connected to power/ground planes with degassing holes. The mutual inductance between capacitor pads, vias, and power/ground planes are completely modeled. Through optimized via and capacitor pads placement designs, our modeling results show that the mutual inductance drastically changes the total loop inductance as compared to the self-inductance of the capacitor. To validate the integrated modeling method, a test package is built. A measurement technique is introduced to evaluate the total loop inductance of the test package with various capacitor form factors and types. The predicted results match well with the measured data. This paper discusses further the usage of the three-dimensional (3-D) integrated model for actual implementation of decoupling capacitors on packages in order to ensure the effectiveness of the capacitors. The first decoupling capacitor placement design on package that we will discuss is the Plastic Pin Grid Array (PPGA) package for Intel´s CPU. Through the three-dimensional (3-D) integrated modeling, the inductance value of the power delivery system with and without capacitors are extracted. It was found that due to the pin-out constraint of CPU PPGA products, as well as unfavorable PPGA package design rules, decoupling capacitors placed in PPGA packages are not effective due to high loop inductance. The second package that we will discuss is the Flip Chip Pin Grid Array (FC-PGA) package, which is for Intel´s future CPU packaging. It is found that the decoupling capacitor placement on the FC-PGA highly improves the performance of the power delivery system. For the same amount of cost, the total loop inductance for FCPGA package decoupling capacitors is found to be 1/9th the total loop inductance for the PPGA package