• DocumentCode
    1372167
  • Title

    Impact of solder pad size on solder joint reliability in flip chip PBGA packages

  • Author

    Mercado, Lei L. ; Sarihan, Vijay ; Guo, Yifan ; Mawer, Andrew

  • Author_Institution
    Digital DNA Labs., Motorola Inc., Tempe, AZ, USA
  • Volume
    23
  • Issue
    3
  • fYear
    2000
  • fDate
    8/1/2000 12:00:00 AM
  • Firstpage
    415
  • Lastpage
    420
  • Abstract
    A variety of parameters impact package reliability. One set of parameters that does not get much attention is the variations in package design that are assembly and vendor related. This study shows that solder pad size is important in solder joint reliability. Differences in solder pad size due to different vendors and processes can affect the reliability considerably. The impact of substrate thickness on package reliability has been shown in finite element stress analysis, moire interferometry experiments, and reliability tests. However, in certain cases, the pad size effect can be so significant that it overrides the impact of substrate thickness. This work indicates that in order to obtain good correlation between predictive engineering results and reliability tests data, this factor should not be ignored. In this study, finite element simulation has been used to quantify the pad size effect on the BGA reliability in the PBGA package. Air-to-air thermal cycling test results were compared with FEM predictions. Optimized pad sizes are discussed and the impact on the solder joint reliability is predicted. Solder pad size effect was found to be a dominant feature in correlating test data with predictions
  • Keywords
    ball grid arrays; finite element analysis; flip-chip devices; integrated circuit packaging; integrated circuit reliability; moire fringes; plastic packaging; soldering; stress analysis; electronic packaging; finite element model; flip-chip PBGA package; moire interferometry; solder joint reliability; solder pad size; stress analysis; substrate thickness; thermal cycling; Assembly; Data engineering; Finite element methods; Flip chip; Interferometry; Occupational stress; Packaging; Reliability engineering; Soldering; Testing;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/6040.861555
  • Filename
    861555