A New DAC Mismatch Shaping Technique for Sigma–Delta Modulators

Author

Aboudina, Mohamed ; Razavi, Behzad

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

Volume

57

Issue

12

fYear

2010

Firstpage

966

Lastpage

970

Abstract

A new ΣΔ modulator architecture that shapes digital-to-analog converter (DAC) mismatches in a manner similar to quantization noise shaping is proposed, allowing operation with low oversampling ratios, high-resolution quantizers, and compact logic. It is shown that the proposed architecture entails a smaller feedback logic delay than data-weighted-averaging techniques, providing a fourfold delay reduction for a 6-bit feedback DAC. The front-end integrator implementation also exhibits 25% less kT/C noise than conventional architectures.

Keywords

digital-analogue conversion; quantisation (signal); sigma-delta modulation; ΣΔ modulator architecture; 6-bit feedback DAC; DAC mismatch shaping technique; compact logic; data weighted averaging; digital-to-analog converter mismatch; feedback logic delay; fourfold delay reduction; high-resolution quantizer; quantization noise shaping; sigma-delta modulators; Analog-digital conversion; Capacitors; Digital-analog conversion; Pulse shaping methods; Sigma delta modulation; Digital-to-analog converter (DAC) mismatch shaping; high-speed analog-to-digital converter (ADC); sigma–delta modulators;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2083172

Filename

5624575