DocumentCode
1372360
Title
Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations
Author
Shigyo, Naoyuki
Author_Institution
Syst. LSI Design Dept., Toshiba Corp., Yokohama, Japan
Volume
47
Issue
9
fYear
2000
fDate
9/1/2000 12:00:00 AM
Firstpage
1740
Lastpage
1744
Abstract
This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed
Keywords
capacitance; delays; integrated circuit interconnections; C delay; Cu; RC delay; critical dimension variation; design model; fringing capacitance; interconnect capacitance; process fluctuations; Delay; Fluctuations; Guidelines; Integrated circuit interconnections; Parasitic capacitance; Performance analysis; Process design; Robustness; Very large scale integration; Wiring;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.861585
Filename
861585
Link To Document