Analysis and Digital Implementation of Cascaded Delayed-Signal-Cancellation PLL

Phase-locked loop (PLL) is usually required to detect grid phase angle in grid-tied converters. Conventional PLL schemes have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To overcome this challenge, a generalized delayed-signal-cancellation (DSC) operator is proposed recently to form cascaded DSC (CDSC) operator to eliminate arbitrary harmonics. With the CDSC operator, the conditioned voltage can be used in PLL loop with very high bandwidth for fast tracking. However, for digital implementation, the CDSC operator may subject to delay-time error, which subsequently leads to residual distortions in the conditioned voltage. In this paper, a thorough analysis of the CDSC operator in both synchronous and stationary reference frames is first conducted. The discretization error during digital implementation due to nonideal system sampling frequency and/or grid-frequency variation is quantified with the proposed concept of relative harmonic gain error. An effective improvement method is then developed that is based on linear interpolation and is effective for all delay-based PLL schemes. Finally, experimental results are obtained to verify the harmonic elimination ability of CDSC in various scenarios and the effectiveness of the interpolation-based digital implementation scheme.