A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

Author

Peng Zhu ; Xinpeng Xing ; Gielen, G.

Author_Institution

Dept. of Elektrotech., KU Leuven, Leuven, Belgium

fYear

2014

fDate

22-26 Sept. 2014

Firstpage

63

Lastpage

66

Abstract

This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO´s distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.

Keywords

CMOS integrated circuits; adders; analogue-digital conversion; low-power electronics; voltage-controlled oscillators; CMOS process; FoM; analog-to-digital converters; bandwidth 40 MHz; closed-loop-based ADC; dual-input VCO-based quantizer topology; low-power multiinput adder; nonlinearity cancellation technique; power 4.98 mW; size 40 nm; word length 12 bit; Adders; Bandwidth; Power harmonic filters; Prototypes; Signal to noise ratio; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th

Conference_Location

Venice Lido

ISSN

1930-8833

Print_ISBN

978-1-4799-5694-4

Type

conf

DOI

10.1109/ESSCIRC.2014.6942022

Filename

6942022