Title :
A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS
Author :
Larie, Aurelien ; Kerherve, Eric ; Martineau, Baudouin ; Knopik, V. ; Belot, Didier
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (PSAT) of 19.9 dBm and a 1-dB compressed output power (P-1dB) of 17.2 dBm while achieving maximum power added efficiency (PAEmax) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm2. To the author´s knowledge, this amplifier presents the highest figure of merit (FoM ITRS) among 60 GHz PAs using silicon technology.
Keywords :
CMOS analogue integrated circuits; field effect MIMIC; low-power electronics; millimetre wave power amplifiers; power combiners; FoM ITRS; PAE; bandwidth 9 GHz; capacitors; common-source pseudodifferential stages; compact transformer-based 8-way power combiner; figure of merit; frequency 60 GHz; gain 32.4 dB; highly linear power amplifier; low power CMOS technology; power added efficiency; power gain; reverse isolation; silicon technology; size 65 nm; small-signal gain; voltage 1.2 V; CMOS integrated circuits; Gain; Power amplifiers; Power combiners; Power generation; Silicon; Transistors; 60 GHz; 65nm CMOS technology; integrated transformer; power amplifier; power combiner;
Conference_Titel :
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
Conference_Location :
Venice Lido
Print_ISBN :
978-1-4799-5694-4
DOI :
10.1109/ESSCIRC.2014.6942050
