A 5b 12.9 µW charge-redistribution phase domain ADC for low power FSK/PSK demodulation

This paper presents a 5 bit charge-redistribution phase domain ADC (PhADC) implemented in 0.18 μm CMOS technology for low power FSK/PSK demodulation. An IQ-assisted conversion algorithm is proposed to avoid the need for an accurate linear combination of in-phase (I) and quadrature (Q) signals with various scaling factors in a conventional zerocrossing algorithm, thus eliminating the power consumption and the phase nonidealities arising from such a linear combination. A PhADC based on a charge-redistribution DAC is demonstrated as a low power implementation of the algorithm due to the energy efficient operation in the charge domain. The prototype achieves an ENOB of 4.85 bit at 1 MS/s, while dissipating 12.9 μW from a 1.2 V supply, leading to a FoM of 1.2 pJ/step.