Title :
High-speed parallel-prefix module 2n-1 adders
Author :
Kalampoukas, Lampros ; Nikolos, Dimitris ; Efstathiou, Costas ; Vergos, Haridimos T. ; Kalamatianos, John
Author_Institution :
Xebeo Commun. Inc., South Plainfield, NJ, USA
fDate :
7/1/2000 12:00:00 AM
Abstract :
A novel parallel-prefix architecture for high speed module 2n -1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures
Keywords :
adders; digital arithmetic; CMOS implementations; carry look-ahead structures; high-speed parallel-prefix module 2n-1 adders; parallel-prefix architecture; Adders; Application software; Circuits; Computer architecture; Concurrent computing; Delay; Fault tolerant systems; Logic; Signal generators; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
