1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS

Author

Abbasi, Shahbaz ; Shabra, Ayman

Author_Institution

Inst. Center for Microsyst., Masdar Inst. of Sci. & Technol., Abu Dhabi, United Arab Emirates

fYear

2014

fDate

22-26 Sept. 2014

Firstpage

355

Lastpage

358

Abstract

A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it´s measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and -3.9dB, and a power consumption of 19mW and 31mW respectively. The input referred noise density is 2.32 and 2.9 nVrms/rHz for the highest and lowest gain settings.

Keywords

CMOS analogue integrated circuits; UHF amplifiers; UHF filters; UHF integrated circuits; low-pass filters; radio receivers; 3rd order lowpass filter; CMOS; LC ladder based filter; baseband section; buffering; filter design; frequency 1.76 GHz; frequency 1.8 GHz; frequency 2.3 GHz; gain 21.6 dB; gain 5.6 dB; mm-wave wireless receiver; power 19 mW; power 31 mW; programmable gain amplifier; size 180 nm; termination; CMOS integrated circuits; Gain; Gain measurement; Inductors; Noise; Noise measurement; Optical filters; LC filter; analog baseband; continuous-time filter;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th

Conference_Location

Venice Lido

ISSN

1930-8833

Print_ISBN

978-1-4799-5694-4

Type

conf

DOI

10.1109/ESSCIRC.2014.6942095

Filename

6942095