Title :
A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS
Author :
Shiyuan Zheng ; Luong, Howard C.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
Abstract :
A single-chip digital polar transmitter integrates an all-digital synthesizer, a PM/AM modulator, and a linearized power amplifier for WCDMA/WLAN. The 1.7~2.5GHz LO signal is generated from an ADPLL together with a ÷1.5 divider to eliminate DCO pulling. A 2-segment ΣΔ phase modulator enhances the PM bandwidth up to 200MHz, and a digital polar amplifier employs AM-replica linearization to eliminate predistortion. The TX measures EVM 4% for a 20MHz-bandwidth 64-QAM while providing a peak output power of 22.1dBm with bit-to-RF efficiency 27.6%.
Keywords :
CMOS integrated circuits; code division multiple access; power amplifiers; quadrature amplitude modulation; radio transmitters; wireless LAN; AM replica linearization; CMOS; DCO pulling; QAM; WCDMA/WLAN digital polar transmitter; digital polar amplifier; digital synthesizer; frequency 1.7 GHz to 2.5 GHz; frequency 200 MHz; linearized PA; linearized power amplifier; low noise ADPLL; single chip digital polar transmitter; size 65 nm; wide band PM/AM modulator; CMOS integrated circuits; Frequency conversion; Frequency modulation; Phase modulation; Phase noise; Switches; Transmitters; ADPLL; digital polar transmitter; linearization; phase modulator; power amplifier;
Conference_Titel :
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
Conference_Location :
Venice Lido
Print_ISBN :
978-1-4799-5694-4
DOI :
10.1109/ESSCIRC.2014.6942100
