Title :
Submicron super TFTs for 3-D VLSI applications
Author :
Hongmei Wang ; Mansun Chan ; Jagar, S. ; Yangyuan Wang ; Ko, P.K.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, gmax=198 mS/mm and an I/sub dast/ of 0.3 mA/μm at V/sub g/-VT=1.5 V, with L/sub G/=0.4 μm and t/sub ox/=110 /spl Aring/. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS.
Keywords :
CMOS integrated circuits; Grain refinement; Recrystallization annealing; Semiconductor device measurement; Thin film transistors; VLSI; 0.4 mum; 1.5 V; 110 angstrom; 198 mS/mm; 3-D VLSI applications; SOI MOSFET; Si-SiO/sub 2/; channel region; controllability; crystallisation; device-to-device variation; double gate CMOS; grain enhancement method; high temperature annealing; large single grain silicon; n-channel super TFT; submicron super TFTs; subthreshold swing; Amorphous silicon; Annealing; Crystallization; Grain boundaries; Grain size; Integrated circuit technology; Nickel; Temperature; Thin film transistors; Very large scale integration;
Journal_Title :
Electron Device Letters, IEEE
