A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS

Author

Shahramian, Shayan ; Carusone, Anthony Chan

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada

fYear

2014

fDate

22-26 Sept. 2014

Firstpage

439

Lastpage

442

Abstract

A half-rate decision feedback equalizer (DFE) with two infinite impulse response (IIR) filters and one discrete-time tap is presented. The two IIR filters have different time constants to cancel the long tail of the pulse response. The discrete-tap cancels the first post-cursor inter-symbol interference term. The system can operate with a low transmit swing of 150mVpp-diff and 24 dB channel loss at the Nyquist frequency while consuming 4.1mW at 10 Gb/s. The receiver, including the DFE, clock buffers and clock phase adjustment, occupies an area of 8,760 μm² and was fabricated in an ST 28nm LP CMOS process.

Keywords

CMOS integrated circuits; IIR filters; channel estimation; clocks; decision feedback equalisers; interference suppression; intersymbol interference; low-power electronics; receivers; 2-IIR-1-discrete-tap DFE; LP CMOS process; Nyquist frequency; bit rate 10 Gbit/s; channel loss; clock buffers; clock phase adjustment; discrete-time tap; half-rate decision feedback equalizer; infinite impulse response filters; post-cursor intersymbol interference cancellation; power 4.1 mW; pulse response; size 28 nm; time constants; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Latches; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th

Conference_Location

Venice Lido

ISSN

1930-8833

Print_ISBN

978-1-4799-5694-4

Type

conf

DOI

10.1109/ESSCIRC.2014.6942116

Filename

6942116