Title :
Clock-delayed domino for dynamic circuit design
Author :
Yee, Gin ; Sechen, Carl
Author_Institution :
Sun Microsyst., Palo Alto, CA, USA
Abstract :
Clock-delayed (CD) domino is a self-timed dynamic logic family developed to provide single-rail gates with inverting or noninverting outputs. CD domino is a complete logic family and is as easy to design with as static CMOS circuits from a logic design and synthesis perspective. Design tools developed for static CMOS are used as part of a methodology for automating the design of CD domino circuits. The methodology and CD domino´s characteristics are demonstrated in the design of a 32-b carry look-ahead adder. The adder was fabricated with MOSIS´s 0.8-/spl mu/m CMOS process with scalable CMOS design rules that allow a 1.0-/spl mu/m drawn gate length. Measurements of the adder show a worst case addition of 2.1 ns. The CD domino adder is 1.6/spl times/ faster than a dual-rail domino adder designed with the same cell library and technology.
Keywords :
CMOS logic circuits; adders; carry logic; clocks; delays; integrated circuit design; logic CAD; 0.8 micron; 1.0 micron; 2.1 ns; 32 bit; CMOS process; carry look-ahead adder; clock-delayed domino; dynamic circuit design; inverting outputs; logic design; noninverting outputs; scalable CMOS design rules; self-timed dynamic logic family; single-rail gates; Adders; CMOS logic circuits; CMOS process; Circuit synthesis; Clocks; Delay; Logic circuits; Logic design; Logic functions; Pulse inverters;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
