Peak power estimation of VLSI circuits: new peak power measures

Author

Hsiao, Michael S. ; Rudnick, Elizabeth M. ; Patel, James H.

Author_Institution

Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

Volume

8

Issue

4

fYear

2000

Firstpage

435

Lastpage

439

Abstract

New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models.

Keywords

VLSI; circuit analysis computing; delays; genetic algorithms; integrated circuit design; parameter estimation; sequential circuits; K2 tool; VLSI circuits; automatic generation; automatic procedure; delay models; functional vector loop; genetic algorithm framework; lower bounds; peak power dissipation; peak power estimation; power consumption; sequential circuits; vector sequences generat; Combinational circuits; Delay estimation; Energy consumption; Power dissipation; Power generation; Power measurement; Sequential circuits; Switches; Switching circuits; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.863624

Filename

863624