DocumentCode
1374223
Title
Effect of Stress-Induced Degradation in LDMOS
Noise Characteristics
Author
Mahmud, M.I. ; Çelik-Butler, Z. ; Hao, P. ; Srinivasan, P. ; Hou, F. ; Amey, B.L. ; Pendharkar, S.
Author_Institution
Dept. of Electr. Eng., Univ. of Texas, Arlington, TX, USA
Volume
33
Issue
1
fYear
2012
Firstpage
107
Lastpage
109
Abstract
Low-frequency noise in double reduced-surface-field lateral-double-diffused-MOS devices has been measured, and the effect of dc stressing is analyzed. The noise components contributing from the extended drain regions under the gate and field oxides were differentiated from the channel noise by a series of experimental and analytical techniques. The effect of voltage stressing on each noise component was investigated. Trapped-charge carrier fluctuations due to Si/SiO2 interface traps in the overlap region in the extended drain as well as in the channel were found to be the dominant source of noise. The bulk resistance fluctuations in the extended drain region under the field oxide were found to be insignificant. High-voltage stressing caused an increase in the interface traps, thus increasing both the extended drain overlap resistance and the noise.
Keywords
1/f noise; MOS integrated circuits; LDMOS 1/f noise characteristics; bulk resistance fluctuations; dc stressing; double reduced-surface-field lateral-double-diffused-MOS devices; extended drain overlap resistance; interface traps; low-frequency noise; stress-induced degradation; trapped-charge carrier fluctuations; Degradation; Electrical resistance measurement; Logic gates; Noise; Resistance; Silicon; Stress; $hbox{1}/f$ noise; High-voltage stressing; lateral double diffused MOS (LDMOS); reduced surface field (RESURF);
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2011.2171473
Filename
6078391
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