Title :
Analysis and future trend of short-circuit power
Author :
Nose, Koichi ; Sakurai, Takayasu
Author_Institution :
Inst. of Ind. Sci., Tokyo Univ., Japan
fDate :
9/1/2000 12:00:00 AM
Abstract :
A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, PS, caused by the scaling in relation to the charging and discharging power, PD , is discussed and it is shown that basically power ratio, PS /(PD+PS), will not change with scaling if V TH/VDD is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates
Keywords :
CMOS logic circuits; VLSI; logic design; logic gates; low-power electronics; CMOS gates; NAND gates; channel length; charging power; closed-form expression; complex gates; discharging power; load capacitance; scaling; series-connected MOSFET structures; short-channel effects; short-circuit power dissipation; Capacitance; Closed-form solution; Inverters; MOS devices; MOSFET circuits; Nose; Power MOSFET; Power dissipation; Threshold voltage; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
