Analysis and future trend of short-circuit power

Author

Nose, Koichi ; Sakurai, Takayasu

Author_Institution

Inst. of Ind. Sci., Tokyo Univ., Japan

Volume

19

Issue

9

fYear

2000

fDate

9/1/2000 12:00:00 AM

Firstpage

1023

Lastpage

1030

Abstract

A closed-form expression for short-circuit power dissipation of CMOS gates is presented which takes short-channel effects into consideration. The calculation results show good agreement with the SPICE simulation results over wide range of load capacitance and channel length. The change in the short-circuit power, P_S, caused by the scaling in relation to the charging and discharging power, P_D, is discussed and it is shown that basically power ratio, P_S/(P_D+P_S), will not change with scaling if V _TH/V_DD is kept constant. This paper also handles the short-circuit power of series-connected MOSFET structures which appear in NAND and other complex gates

Keywords

CMOS logic circuits; VLSI; logic design; logic gates; low-power electronics; CMOS gates; NAND gates; channel length; charging power; closed-form expression; complex gates; discharging power; load capacitance; scaling; series-connected MOSFET structures; short-channel effects; short-circuit power dissipation; Capacitance; Closed-form solution; Inverters; MOS devices; MOSFET circuits; Nose; Power MOSFET; Power dissipation; Threshold voltage; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.863642

Filename

863642