Title :
A fast signature computation algorithm for LFSR and MISR
Author :
Lin, Bin-Hong ; Shieh, Shao-Hui ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fDate :
9/1/2000 12:00:00 AM
Abstract :
A multiple-input signature register (MISR) computation algorithm for fast signature simulation is proposed. Based on the table look-up linear compaction algorithm and the modularity property of a single-input signature register (SISR), some new accelerating schemes-partial-input look-up tables and flying state look-up tables-are developed to boost the signature computation speed. Mathematical analysis and simulation results show that this algorithm has an order of magnitude speedup without extra memory requirement compared with the original linear compaction algorithm. Though this algorithm is derived for SISR, a simple conversion scheme exists that can convert internal-EXOR MISR to SISR. Consequently, fast MISR signature computation can be done
Keywords :
built-in self test; circuit analysis computing; computational complexity; fault simulation; integrated circuit testing; logic testing; shift registers; table lookup; BIST; LFSR; LUT methods; MISR computation algorithm; accelerating schemes; complexity analysis; conversion scheme; fast signature computation algorithm; fast signature simulation; flying state lookup tables; linear feedback shift registers; modularity property; multiple-input signature register; partial-input lookup tables; signature computation speed; single-input signature register; table lookup linear compaction algorithm; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Compaction; Computational modeling; Electrical fault detection; Registers; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
