DocumentCode :
1374300
Title :
Star test: the theory and its applications
Author :
Kun-Han Tsai ; Rajski, J. ; Marek-Sadowska, M.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Volume :
19
Issue :
9
fYear :
2000
Firstpage :
1052
Lastpage :
1064
Abstract :
In this paper, we introduce a hierarchical test set structure called star test, derived from the experimental observation of the fault clustering phenomena. Based on the concept of star test, two applications are studied: one applied to built-in-self-test (BIST); the other to automatic test pattern generation (ATPG). First, a very high quality and low-cost BIST scheme, named STAR-BIST is proposed. Experimental results have demonstrated that a very high fault coverage can be obtained without any modification of the logic under test, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. Second, an efficient test generator, named STAR-ATPG, is developed which speeds up the ATPG performance by a factor of up to five for large industrial circuits.
Keywords :
Automatic test pattern generation; Built-in self test; Design for testability; Integrated circuit testing; Logic testing; Probability; ATPG; DFT; STAR-ATPG algorithm; STAR-BIST; automatic test pattern generation; built-in-self-test; fault clustering analysis; hierarchical test set structure; high fault coverage; low-cost BIST scheme; star test; test generator; Associate members; Automatic test pattern generation; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Hardware; Logic testing; Sequential analysis; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.863645
Filename :
863645
Link To Document :
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