• DocumentCode
    1374306
  • Title

    Improving symbolic reachability analysis by means of activity profiles

  • Author

    Cabodi, Gianpiero ; Camurati, Paolo ; Quer, Stefano

  • Author_Institution
    Dipt. di Autom. e Inf., Politecnico di Torino, Italy
  • Volume
    19
  • Issue
    9
  • fYear
    2000
  • fDate
    9/1/2000 12:00:00 AM
  • Firstpage
    1065
  • Lastpage
    1075
  • Abstract
    Symbolic techniques have undergone major improvements in the last few gears. Nevertheless, applications are still limited by memory size and time constraints. As a consequence, extending their applicability to larger and real circuits is still a key issue. Within this framework, we introduce “activity profiles” as a novel technique to characterize finite state machines described by their transition relation. In our methodology, a “learning phase” is used to collect activity measures. They are gathered, in an inexpensive way, for each binary decision diagram node of the transition relation. They indicate the activity the node has been involved in, as an estimate of its correlation with space and/or time costs. The above information can be used for several purposes. In particular, we present an application of activity profiles in the field of reachability analysis, to enhance memory and time performance of traversals. More specifically, we use transition relation subsetting in order to traverse the state transition graph in a nonpurely breadth-first, guided and multistep fashion. Comparisons with other state-of-the-art approaches show that our sequence of partial traversals produces “best-ever” results for all the large benchmarks analyzed
  • Keywords
    binary decision diagrams; circuit analysis computing; finite state machines; formal verification; reachability analysis; symbol manipulation; BDD node; FSM characterization; activity profiles; binary decision diagram node; finite state machines; state transition graph; symbolic reachability analysis; transition relation subsetting; Automata; Binary decision diagrams; Boolean functions; Circuits; Costs; Data structures; Formal verification; Phase measurement; Reachability analysis; Time factors;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.863646
  • Filename
    863646