DocumentCode :
1375192
Title :
Architectural considerations for a self-timed decoupled processor
Author :
Richardson, W.F. ; Brunvand, E.
Author_Institution :
Dept. of Comput. Sci., Utah State Univ., Logan, UT, USA
Volume :
143
Issue :
5
fYear :
1996
fDate :
9/1/1996 12:00:00 AM
Firstpage :
251
Lastpage :
258
Abstract :
Self-timed processor designs offer several advantages over traditional synchronous designs. Further, when an asynchronous philosophy is incorporated at every stage of the design, the microarchitecture is more closely linked to the basic structures of the self-timed circuits themselves, and the resulting processor is quite simple and elegant. The Fred architecture presented here is an example of such a design approach. The self-timed design philosophy results in a powerful and flexible architecture which exhibits significant savings in design effort and circuit complexity. Some of the architectural constraints discovered in the course of the design have simple yet unconventional solutions, which, in turn, provide additional benefits beyond their immediate application
Keywords :
computer architecture; pipeline processing; timing circuits; Fred architecture; architectural considerations; asynchronous philosophy; microarchitecture; self-timed circuits; self-timed decoupled processor;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:19960659
Filename :
537215
Link To Document :
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