Low-Power Spectral-Line Clock Recovery Algorithm for SDR Applications

In this brief, we present a low-complexity digital spectral-line (SL) clock recovery algorithm that is suitable for low-power software-defined radio (SDR) communications. In order to reduce the resource and power consumption, we used a customized integrator to remove the most disruptive SL harmonics. Performance is established in terms of mean-square timing error (MSTE), computational complexity, and power consumption. To assess the viability of the proposed algorithm, the MSTE of the proposed method is compared to that of a typical SL clock recovery algorithm. Furthermore, using a field-programmable gate array platform, we address the computational complexity of the proposed algorithm for implementation in SDR applications. We show that the MSTE for the proposed method is almost the same as that for typical SL clock recovery algorithms while requiring significantly less resources and power.