Low-power, small-footprint gigabit Ethernet-compatible optical receiver circuit in 0.25 μm CMOS

Author

Woodward, T.K. ; Krishnamoorthy, A.V. ; Rozier, R.G. ; Lentine, A.L.

Author_Institution

Lucent Technol. Bell Labs., Holmdel, NJ, USA

Volume

36

Issue

17

fYear

2000

fDate

8/17/2000 12:00:00 AM

Firstpage

1489

Lastpage

1491

Abstract

Experimental results for a gigabit Ethernet-compatible photo-receiver circuit generating CMOS logic level are presented. A single-ended preamplifier is combined with a multi-stage differential postamplifier with inverse scaling to increase bandwidth. Circuits are realised in 0.25 μm CMOS, dissipating 26 mW or less. The analogue portion of the receiver operates at 2 μA average input current at 1.25 Gbit/s, increasing to ~10 μm when CMOS levels are generated. A maximum speed of 2.1 Gbit/s is reported for the analogue portion

Keywords

CMOS integrated circuits; integrated optoelectronics; logic circuits; optical fibre LAN; optical receivers; preamplifiers; 0.25 μm CMOS; 0.25 mum; 1.25 Gbit/s; 2 muA; 2.1 Gbit/s; 26 mW; CMOS levels; CMOS logic level; analogue portion; gigabit Ethernet-compatible photo-receiver circuit; input current; inverse scaling; low-power small-footprint gigabit Ethernet-compatible optical receiver circuit; multi-stage differential postamplifier; single-ended preamplifier;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:20000935

Filename

865056