Title :
Design and implementation of a GaAs systolic floating-point processing element
Author :
Beaumont-Smith, A. ; Marwood, W. ; Lim, C.C. ; Eshraghian, K.
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
fDate :
9/1/1996 12:00:00 AM
Abstract :
The design and layout of a prototype single precision systolic floating-point processing element (PE) is described. It is intended for use in a class of systolic array processors which perform matrix computations. Each PE is constructed from a digit-serial systolic ring of four programmable cells and performs floating-point multiplication and accumulation. A single PE has been fabricated in a 0.8 μm gallium arsenide E/D MESFET process and has a maximum clock speed of 300 MHz. The chip can be configured into a 16×16 array to achieve a peak computation rate of 2.5 GFLOPS
Keywords :
III-V semiconductors; floating point arithmetic; gallium arsenide; systolic arrays; 0.8 micron; 2.5 GFLOPS; 300 MHz; E/D MESFET process; GaAs systolic floating-point processing element; accumulation; design; digit-serial systolic ring; matrix computations; programmable cells; systolic array processors;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
DOI :
10.1049/ip-cdt:19960635
