Title :
The Gmicro/300 32-bit microprocessor
Author :
Kitahara, Takeshi ; Satoh, Taizo
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
fDate :
6/1/1990 12:00:00 AM
Abstract :
A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300´s pipeline structure, its other one-cycle structures, and the effects of using internal caches are discussed.<>
Keywords :
microprocessor chips; 32 bit; Gmicro/300 32-bit microprocessor; TRON architecture specification; cache memories; internal caches; memory operand; one-cycle structures; register operand; Cache memory; Clocks; Microprocessors; Pipelines; Reduced instruction set computing; Registers;
Journal_Title :
Micro, IEEE
