• DocumentCode
    1376712
  • Title

    A selective epitaxial SiGe/Si planar photodetector for Si-based OEIC´s

  • Author

    Tashiro, Tsutomu ; Tatsumi, Toru ; Sugiyama, Mitsuhiro ; Hashimoto, Toshiki ; Morikawa, Takenori

  • Author_Institution
    ULSI Device Dev. Lab., NEC Corp., Kanagawa, Japan
  • Volume
    44
  • Issue
    4
  • fYear
    1997
  • fDate
    4/1/1997 12:00:00 AM
  • Firstpage
    545
  • Lastpage
    550
  • Abstract
    A P-i-N SiGe/Si superlattice photodetector with a planar structure has been developed for Si-based opto-electronic integrated circuits. To make the planar structure, a novel SiGe/Si selective epitaxial growth technology which uses cold wall ultrahigh-vacuum/chemical vapor deposition has been newly developed. The P-i-N planar SiGe/Si photodetector has an undoped 30-Å Si0.9Ge0.1/320-Å Si, 30 periods, superlattice absorption layer, a 0.1-μm P-Si buffer layer, and a 0.2-μm P+-Si contact layer on a bonded silicon-on-insulator (ηext). The bonded SOI is used to increase the external quantum efficiency (ηext) of the photodetector. Moreover, a 63-μm deep/128-μm wide trench, to achieve simple and stable coupling of an optical fiber to the photodetector, is formed in the silicon chip. The P-i-N planar photodetector exhibits a high ηext of 25-29% with a low dark current of 0.5 pA/μm2 and a high-frequency photo response of 10.5 GHz at λ=0.98 μm
  • Keywords
    Ge-Si alloys; integrated optoelectronics; p-i-n photodiodes; photodetectors; semiconductor materials; semiconductor superlattices; silicon-on-insulator; vapour phase epitaxial growth; 0.98 micron; 10.5 GHz; 25 to 29 percent; P-i-N superlattice photodetector; Si0.9Ge0.1-Si; bonded SOI; cold wall ultrahigh-vacuum/chemical vapor deposition; dark current; external quantum efficiency; optical fiber coupling; optoelectronic integrated circuit; planar structure; selective epitaxial growth; silicon OEIC chip; Bonding; Chemical technology; Epitaxial growth; Germanium silicon alloys; Integrated circuit technology; PIN photodiodes; Photodetectors; Silicon germanium; Superlattices; Time of arrival estimation;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.563356
  • Filename
    563356