Zero-Sleep-Leakage Flip-Flop Circuit With Conditional-Storing Memristor Retention Latch

Author

Jung, Chul-Moon ; Jo, Kwan-Hee ; Lee, Eun-Sub ; Vo, Huan Minh ; Min, Kyeong-Sik

Author_Institution

Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea

Volume

11

Issue

2

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

360

Lastpage

366

Abstract

In this paper, two new zero-sleep-leakage flip-flop (F-F) circuits are proposed to make the sleep leakage literally zero. At the sleep-in time, the F-F´s data are transferred to memristor retention latch; thus, the F-F can be completely cutoff from the external power supply saving the energy leak during the sleep time. The conditional storing circuit in the F-F (type-2) can reduce switching power by 87% in storing the data than the F-F (type-1). And, the crossover time of the F-F (type-2) is shortened by 97% than the F-F (type-1).

Keywords

electrical faults; energy conservation; flip-flops; memristors; F-F cutoff; F-F data; conditional storing circuit; conditional-storing memristor retention latch; energy leak; external power supply saving; sleep time; switching power reduction; zero-sleep-leakage flip-flop circuit; Anodes; Latches; Master-slave; Memristors; Resistance; Switching circuits; Writing; Conditional-storing technique; memristor retention latch; power gating scheme; zero-sleep-leakage flip-flop;

fLanguage

English

Journal_Title

Nanotechnology, IEEE Transactions on

Publisher

ieee

ISSN

1536-125X

Type

jour

DOI

10.1109/TNANO.2011.2175943

Filename

6082452