Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign

The design and implementation of a lossless compression system for hyperspectral images on a processor-plus-field-programmable gate array (FPGA)-based embedded platform. Software execution time of compression algorithm was profiled first to conclude the decision of accelerating the most time consuming interband prediction module by hardware realization. Efficient algorithm to hardware mapping led to a high throughput accelerator design in FPGA capable of processing 16.5 M pixels/s. A set of optimization techniques were applied systematically to enhance the overall system performance. These include a hierarchical memory access scheme to resolve the bus bandwidth limitation, DMA assisted data transfers to shorten the hardware/software (HW/SW) communication, and various coding style and compiler options to optimize the software execution. The final result shows a 21 speed-up compared to a purely software implementation and the performance was actually bounded by the software section in realizing an entropy coder. A 27 speed-up can be achieved if a simplified coder is used.