Title :
Compact charge-based 4 bit flash ADC circuit architecture for ANN applications
Author :
Schmid, A. ; Leblebici, Y. ; Mlynek, D.
Author_Institution :
Integrated Syst. Center, Fed. Inst. of Technol., Lausanne, Switzerland
fDate :
4/16/1998 12:00:00 AM
Abstract :
A charge based flash analogue-digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4 bit ADC has been realised with an 0.8 μm double-poly process, and tested to confirm its linearity over the full range and a conversion speed of 10 Msamples/s
Keywords :
analogue-digital conversion; neural chips; 0.8 micron; 4 bit; ANN; analogue-digital converter; artificial neural network; charge based flash ADC circuit architecture; compactness; conversion speed; double-poly process; linearity;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19980592
