DocumentCode
1378970
Title
Design and analysis of asynchronous adders
Author
Johnson, D. ; Akella, V.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Volume
145
Issue
1
fYear
1998
fDate
1/1/1998 12:00:00 AM
Firstpage
1
Lastpage
8
Abstract
An asynchronous adder can take advantage of the shorter carry propagation chains that occur in practice and exhibit a data-dependent computation delay. Basically, an asynchronous adder has a mechanism to announce early completion by detecting when it is done. Such an adder is extremely useful in asynchronous implementation of computing structures. In this paper we evaluate the designs tradeoffs of well-known asynchronous adder configurations based on ripple-carry and carry lookahead topologies. We show that, using complex gates, carry lookahead asynchronous adders can be realised that outperform ripple-carry asynchronous adders, both in average-case delay and worst-case delay without increasing the area and power consumption. The underlying timing assumptions and applications of the adder in asynchronous pipelines (micropipelines) are also discussed
Keywords
adders; asynchronous adders; average-case delay; carry propagation chains; data-dependent computation delay; worst-case delay;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings -
Publisher
iet
ISSN
1350-2387
Type
jour
DOI
10.1049/ip-cdt:19981770
Filename
675536
Link To Document