Efficient bipartitioning algorithm for size-constrained circuits

A novel module-migration bipartitioner (MMP) for VLSI circuits is proposed. MMP uses an efficient module migration process, which can relax the size constraints temporarily and intensify the capability of escaping from local optima, as its iterative improvement mechanism. Besides evaluating the same module gain when performing the Fiduccia-Mattheyses (FM) algorithm for selecting the module to move, MMP also examines the connection strengths between modules, thus capturing more global implications of module moving. Moreover, MMP is robust with a self-adjusted probabilistic function set which can reduce the sensitivity of some key parameters. Experiments on circuits allowing different deviations from exact bipartition show that MMP is stable on solution quality and that it not only performs much better than FM, but also outperforms many state-of-the-art bipartitioners