Title :
Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling
Author :
Kauppila, Jeffrey S. ; Haeffner, Timothy D. ; Ball, Dennis R. ; Kauppila, Amy V. ; Loveless, T. Daniel ; Jagannathan, Srikanth ; Sternberg, Andrew L. ; Bhuva, Bharat L. ; Massengill, Lloyd W.
Author_Institution :
Inst. for Space & Defense Electron. (ISDE), Vanderbilt Univ., Nashville, TN, USA
Abstract :
A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.
Keywords :
CMOS logic circuits; circuit layout; flip-flops; bulk CMOS flip-flops; circuit-level layout-aware single-event sensitive-area analysis; compact modeling; single-event upset; CMOS integrated circuits; Circuit simulation; Flip-flops; Integrated circuit modeling; Latches; Layout; Radiation effects; SPICE; Single event upset; CMOS integrated circuits; Charge sharing; SPICE; circuit modeling; circuit simulation; compact models; flip-flops; latches; radiation effects; single-event upset (SEU);
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2011.2172692
