Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance

Adding on-chip decoupling capacitance has become a popular method to reduce dI/dt noise in integrated circuits. The most area-efficient realization of on-chip capacitance in a standard CMOS process is to use the gate capacitance of MOS transistors. In this paper, the inevitable parasitic resistance of an MOS transistor is estimated, which is important for two reasons. The resistive noise caused by this parasitic must be kept low, and, if properly sized, this resistance can be used to dampen potential resonance oscillations