Noise margin enhancement in GaAs ROM´s using current mode logic

Author

López, J.F. ; Sarmiento, R. ; Eshraghian, K. ; Núñez, A.

Author_Institution

Centre for Appl. Microelectron., Univ. of Las Palmas, Gran Canaria, Spain

Volume

32

Issue

4

fYear

1997

fDate

4/1/1997 12:00:00 AM

Firstpage

592

Lastpage

597

Abstract

Two different techniques that allow the implementation of embedded ROMs using a conventional GaAs MESFET technology are presented. The first approach is based on a novel circuit structure named low leakage current FET circuit (L2FC), which reduces significantly subthreshold currents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs ROM´s because of its degradation as the number of word lines is increased. A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively. The results demonstrate the effectiveness of these techniques and their significance toward improving the noise margin

Keywords

III-V semiconductors; MESFET integrated circuits; current-mode logic; delays; field effect memory circuits; gallium arsenide; integrated circuit noise; leakage currents; read-only storage; very high speed integrated circuits; 1 ns; 2 Kbit; 2 ns; 5 Kbit; GaAs; III-V semiconductors; L2FC; MESFET technology; ROM; current mode logic; delays; low leakage current FET circuit; noise margin enhancement; pseudo current mode logic; subthreshold currents; word lines; Circuit noise; Degradation; FET circuits; Gallium arsenide; Leakage current; Logic; MESFETs; Noise level; Read only memory; Subthreshold current;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.563683

Filename

563683