Title :
Substrate coupling evaluation in BiCMOS technology
Author :
Casalta, Juan M. ; Aragonès, Xavier ; Rubio, Antonio
Author_Institution :
Dept. d´´Eng. Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
4/1/1997 12:00:00 AM
Abstract :
The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-μm BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring
Keywords :
BiCMOS integrated circuits; crosstalk; integrated circuit measurement; integrated circuit noise; integrated circuit packaging; mixed analogue-digital integrated circuits; 3 micron; BiCMOS technology; bipolar junction transistor; buried layer doping; collector resistance; common-collector biasing; common-emitter biasing; guard ring; inverter gates; noise dependence; substrate coupling; substrate coupling evaluation; switching noise; transistor size; BiCMOS integrated circuits; CMOS technology; Circuit noise; Circuit simulation; Coupling circuits; Crosstalk; Packaging; Paper technology; Silicon on insulator technology; Substrates;
Journal_Title :
Solid-State Circuits, IEEE Journal of
