Title :
Design methodology for a large communication chip
Author :
Clauberg, Rolf ; Buchmann, Peter ; Herkersdorf, Andreas ; Webb, David J.
Author_Institution :
IBM Res. Div., Ruschlikon, Switzerland
Abstract :
The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains, it also couples a large digital design to a mixed-signal part in physical design
Keywords :
finite state machines; hardware-software codesign; logic CAD; digital design; formal verification; large communication chip; static timing analysis; Analytical models; Asynchronous transfer mode; Clocks; Design methodology; Formal verification; Hardware design languages; Scalability; Signal analysis; Synchronous digital hierarchy; Timing;
Journal_Title :
Design & Test of Computers, IEEE
