• DocumentCode
    1379435
  • Title

    Design methodology for a large communication chip

  • Author

    Clauberg, Rolf ; Buchmann, Peter ; Herkersdorf, Andreas ; Webb, David J.

  • Author_Institution
    IBM Res. Div., Ruschlikon, Switzerland
  • Volume
    17
  • Issue
    3
  • fYear
    2000
  • Firstpage
    86
  • Lastpage
    94
  • Abstract
    The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains, it also couples a large digital design to a mixed-signal part in physical design
  • Keywords
    finite state machines; hardware-software codesign; logic CAD; digital design; formal verification; large communication chip; static timing analysis; Analytical models; Asynchronous transfer mode; Clocks; Design methodology; Formal verification; Hardware design languages; Scalability; Signal analysis; Synchronous digital hierarchy; Timing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.867899
  • Filename
    867899
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1379435